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 Logic Synthesis and Verification - COMP4002
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Campus: Kensington Campus
 
 
Career: Undergraduate
 
 
Units of Credit: 6
 
 
Contact Hours per Week: 4
 
 
Enrolment Requirements:
 
 
Prerequisite: COMP9022 or COMP2021.
 
 
Offered: To be advised
 
 
Fee Band: 2
 
  

Description

The first part of the course will cover fundamental data structures and algorithms for logic reasoning. Next we will discuss essential concepts of combinational circuit optimization (two-level and multi-level synthesis, technology-independent optimization, technology mapping), sequential circuit optimization (state encoding, retiming), timing analysis, and testing. The last part of the course will cover selected verification topics to the extent that they are of practical importance for the design of digital systems.

For each topic the theoretical foundations are discussed and practical implementation details are presented. Students will be required to complete weekly homework assignments. Further, during the weekly seminars each student will present a published paper, which elaborates on a topic covered in class. The homework includes programming assignments, which will enable the student to apply the class material in practice.

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